Designing a RISC-V Processor Core
This blog series describes the process of creating a a small RISC-V processor core using SystemVerilog hardware definition language. Each post will be a small tutorial describing the models, testbench and architecture as well as the code to design these and setup steps required to do simulation. We are going to be using open source cycle accurate simulator Verilator in this series. If you want you can use any other simulator capable of running SystemVerilog. In that case you can just skip over the steps describing verilator related steps. The source code explained in each blog post will be available as separate branches in this repository.
We will start with implementing just the RV32I instruction set of the RISC-V specification. We will mostly stick to getting a minimum correct implementation done first. This means we will have only the machine mode in our design and will not worry about the user, supervisor or hypervior modes. We will also focus on a 32 bit implementation only for now. After getting a basic correct processor core implemented, I will either go into more system level implementation details.
Simulating the Skeleton of a Processor Core
The first step in creating our own processor core is to create the testbench, the models and to setup the environment to simulate our design in. To simulate our processor core, we need to instantiate it at a top level from where we can apply different stimulus (or inputs) to the core and monitor the outputs to verify the correctness of our design. Read More»
Implementing our First Instruction
For the next step in designing our processor core, we are going to go head in into implementing our first instruction. This post looks at just one instruction (the R-Type ADD), and implements it from start to end. It will first assume no pipeline stage conflict, and later implement a stalling mechanism incase a conflict is found. Read More»
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