Advent of Code in Verilog: A Hardware Design Challenge

Introduction

The holiday season is upon us, and for many developers, that means diving into the festive coding challenges presented by Advent of Code. This year, I've decided to embark on a unique journey – solving the puzzles using Verilog, a hardware description language typically used for designing digital circuits. In this blog post series, I'll take you through my approach to tackling Advent of Code problems in a hardware-centric manner.

What is Advent of Code?

Advent of Code is an annual coding event that unfolds as an advent calendar. Each day, from December 1st to December 25th, participants are presented with a new coding puzzle. These challenges range from algorithmic problem-solving to intricate coding tasks, making it an exciting and intellectually stimulating way to count down to Christmas.

My Goal

This year, my goal is to not just solve the puzzles but to approach them from a hardware design perspective. I aim to create Verilog modules that represent the essence of the problems, solving them in a manner that mirrors how one might design hardware circuits to address real-world problems.

Introducing the Testbench

At the heart of this unique approach is the concept of a testbench – a crucial component in hardware design. In the context of Advent of Code, the testbench becomes the bridge between the problem statement and the Verilog design that solves the problem. It reads the puzzle inputs, provides sequences to the Verilog design module, and validates the outputs. The testbench module will instantiate the synthesizeable, lint clean solution module and provide each character's ASCII code as input on each clock cycle as a 8 bit input on a input port name "char_in". The testbench shall look for "input_ready" signal from the design module and hold a "input_valid" signal high on each clock cycle it is providing a char input. Since the ascii code of '\n' is 10, getting this value would indicate the end of line. At the end of all lines of input a final 10 may be provided followed by making the "input_valid" signal low. When a "output_valid" pulse is recieved back from the design the testbench shall capture the result and print to the terminal. Since in most problems the result is usually a number the result the module will give will be a 64-bit number on a port named "result".

At the core of this innovative approach lies the concept of a testbench – a fundamental element in hardware design. In the realm of Advent of Code, the testbench serves as the crucial link between the problem statement and the Verilog design responsible for problem-solving. It takes charge of reading puzzle inputs, feeding sequences to the Verilog design module, and validates the ensuing outputs.

Within the testbench module, the synthesizable and lint-clean solution module is instantiated. The testbench starts providing the input sequence only when the "input_ready" output port of the design is high. The input to this design module involves presenting each character's ASCII code as an 8-bit input via a port named "char_in" on every clock cycle while also asserting an "input_valid" signal high, signifying the validity of a character input during that clock cycle.

Notably, to indicate the end of a line, the testbench strategically utilizes the ASCII code for a newline character ('\n'), which is 10. Once the end of input file detected, a final 10 may be provided, and subsequently, the "input_valid" signal is lowered. This approach reduces complexity on testbench design based on the typical inputs of the advent of code.

After dispatching the input sequences, the testbench monitors the "output_valid" pulse from the design module. Upon receipt of this signal, it promptly captures the result and prints it to the terminal. Given that many problems culminate in a numerical result, the design module outputs a 64-bit number, relayed through a 64 bit port named "result."

Stay Tuned!